We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, enabling everything from self-driving cars to advanced learning machines. As the global leader in EDA tools, semiconductor IP, and silicon engineering solutions, we empower the creation of the world’s most advanced chips across AI/ML, high-performance computing, automotive, cloud, and mobile applications. Within our division, we develop and deliver interface subsystems that power industry-leading SoCs. Join us to transform the future through continuous technological innovation and world-class engineering excellence.
You Are:
You are an enthusiastic engineer who thrives at the intersection of various interface IPs. Your analytical mindset and collaborative spirit drive you to solve complex technical challenges that shape the future of connectivity.
You are passionate about deepening your expertise and excited by the prospect to work on advanced DDR/HBM/PCIe/UCIe/Ethernet/UALink IP integration deployed in the most innovative SoCs. You value technical mastery, teamwork, mentorship, and the continuous pursuit of innovation. Your curiosity leads you to understand diverse interface IPs, and you ensure the highest standards of silicon performance through meticulous attention to detail. Navigating simulation environments and debugging challenging issues is second nature to you, and you excel at collaborating with teams across the globe.
What You’ll Be Doing:
• Technically leading and driving ownership of critical areas of verification alongside a team of talented verification engineers.
• Defining, implementing, and tracking comprehensive verification test plans to ensure robust coverage and quality.
• Specifying, building, enhancing, and maintaining state-of-the-art Subsystem top-level UVM-based System Verilog testbenches, in
📌 ASIC Digital Design, Sr Staff Engineer (Noida)
🏢 Synopsys
📍 Noida
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