VLSI Design For Testability - DFT (India)

VLSI Design For Testability - DFT (India)

14 Oct
|
TRIGENT SOFTWARE PRIVATE
|
India

14 Oct

TRIGENT SOFTWARE PRIVATE

India

Skills:

DFT

Scan Insertion

Scan Compression

ATPG Generation & Debug

DFT Rule Checks (DRC)

Coverage Analysis & Closure

Boundary Scan / JTAG

MBIST Exposure preferred

Full-chip and Subsystem DFT Integration

Tools

Siemens Tessent

Synopsys Prime Time

Synopsys Fusion Compiler (FC)

Unix/Linux Setting

Tcl / Perl / Python Scripting

Description:

- Overall 5+ years of relevant experience in Sentinel One EDR tool

- Design, implement, and manage Sentinel One EDR policies, sites, groups, and configurations to ensure effective endpoint protection.

- Perform onboarding of endpoints (servers, workstations, and other assets) into Sentinel One console as per approved scope.

- Coordinate agent deployment, upgrades, and integrations with endpoint, server, GCP, VMware, JAMF, Intune, and application teams.

- Monitor agent health, connectivity, protection status, and endpoint visibility to ensure full coverage.

- Conduct continuous threat monitoring and analysis,



including detections, alerts, unhealthy agents, and remediation activities.

- Configure and maintain security policies (detection modes, exclusions, mitigation actions, and agent settings) based on security requirements.

- Provide Tier 2 and Tier 3 operational support, including troubleshooting agent, console, policy, and upgrade-related issues.

- Manage reporting, documentation, and vendor coordination, including SOPs, dashboards, compliance reporting, and engagement with Sentinel One support for issue resolution and escalations.

- Creating support tickets with OEM/product vendor for troubleshooting bugs, platform issues and root-cause analysis.

- Initiating and participating in OEM driven activities such as platform upgrades and patching.

📌 VLSI Design For Testability - DFT (India)
🏢 TRIGENT SOFTWARE PRIVATE
📍 India

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