Looking for an experienced engineer with strong knowledge of Ser Des and/or DDR circuit design in advanced technology nodes, including FinFET. Must have good understanding of STA concepts and hands-on exposure to Cadence Virtuoso.
Key Responsibilities
- Design and analyze high-speed Ser Des and/or DDR circuits.
- Perform functional analysis, Static Timing Analysis (STA), and electrical sign-off.
- Analyze the impact of process variations on circuit performance.
- Evaluate power-performance trade-offs in high-speed Ser Des designs.
- Execute circuit design activities using AMD tools and support project execution.
- Release PHYs for SoC integration.
Mandatory Skills
- Solid understanding of Ser Des domain and circuit design.
- Good knowledge of Static Timing Analysis (STA) concepts.
- Hands-on exposure to Cadence Virtuoso.
📌 SerDes Circuit Design Engineer (India)
🏢 Sunrisesys
📍 India
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