• Pre-silicon FPGA prototyping and bring-up of the ASA IP digital subsystem.
• Partition the Camera Serializer digital logic for Xilinx VCU128 / Alveo FPGA platform; FPGA-friendly clock domain replacement for PHY-derived clocks
• ASA IP FPGA bring-up: SOC slave bus access, ASEP stream validation, OAM link establishment over cable with reference hardware
• CSI-2 video capture and pixel integrity checks via FPGA-based MIPI sink
• Bring-up script development (Python/ Tcl ); hardware debug (ILA, VIO, ChipScope); lab bring-up with oscilloscope, BERTscope
• Vivado / Vitis; SystemVerilog RTL and Tcl scripting; prior SerDes or MIPI FPGA bring-up experience preferred