Around 5-8 years of minimum exp in Synthesis/Constraints Development and Validation/Timing Closure and Sign-off ( blocks/fullchip) Complete Ownership of Subsystem level STA closure, Includes giving feedback to PnR owner Hands on experience with PrimeTime is must. Good debugging experience on Timing issues and debug the same independently Understanding of timing constraints and constraints related debugging skills Should have worked on lower tech nodes like 7nm , 5nm and below. Understanding of scripting language like tcl, perl etc is added. Should be valuable Team player.
About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.
📌 Technical Lead I - VLSI STA SD (Bengaluru)
🏢 UST
📍 Bengaluru
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