We are seeking a highly skilled Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification and possess a solid background in SystemVerilog (SV) and Universal Verification Methodology (UVM). This role specifically requires expertise in GLS (Gate-Level Simulation).

Key Responsibilities:

IP and SOC Verification
Conduct IP and SOC verification activities to ensure the functionality and correctness of integrated circuits.

SystemVerilog (SV) and UVM Proficiency
Demonstrate solid knowledge of SystemVerilog and Universal Verification Methodology for effective and effective verification processes.

Gate-Level Simulation (GLS)
Proficiency in Gate-Level Simulation is a mandatory requirement for this position.

Qualifications:
Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field.
5 to 12 years of relevant industry experience in IP and SOC verification.
Robust expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM).
Proficiency in Gate-Level Simulation (GLS)

📌 Design Verification Engineer Bengaluru
🏢 Smart Soc Solutions
📍 Bengaluru