Role Overview :

We are seeking a motivated Senior Emulation Engineer to support pre-silicon validation of next-generation processor and SoC products using Synopsys ZeBu emulation platforms. The role involves emulation bring-up, functional validation, debugging, and performance optimization of complex SoC designs.

Key Responsibilities :

- Deploy and validate RTL designs on Synopsys ZeBu emulation platforms.
- Develop and maintain synthesizable testbenches and emulation flows.
- Perform SoC/IP bring-up, functional validation, and debug.
- Support software teams with early boot and system-level validation.
- Analyze failures, debug RTL issues, and drive root-cause resolution.
- Automate emulation and regression flows using scripting languages.

Required Skills :





- 5 - 8 years of experience in ASIC/SoC verification, validation, or emulation.
- Hands-on experience with Synopsys ZeBu platforms.
- Robust knowledge of Verilog/SystemVerilog and UVM.
- Experience with SoC architectures and bus protocols such as AXI, AHB, and APB.
- Proficiency in Python, TCL, or Shell scripting.
- Strong debugging and problem-solving skills.

Preferred Skills :

- Experience with RISC-V processor-based SoCs.
- Exposure to software bring-up, Linux boot, or system-level co-verification.
- Experience with Palladium, Veloce, or FPGA-based prototyping is a plus.

📌 Happiest Minds - Senior ZeBu Emulation Engineer - Pre Silicon Validation (India)
🏢 Happiest Minds Technologies
📍 India