About the Role

SmartSoC Solutions is looking for an experienced and technically strong

RTL Design Lead with 10+ years of experience in RTL design, microarchitecture, and SoC development. The ideal candidate should have strong expertise in

CDC Flow, SerDes, PCIe, AXI protocols, and Firmware integration

, along with proven experience leading RTL design activities from specification to silicon-ready implementation.

Key Responsibilities:

- Lead RTL design and development for complex IPs and SoC subsystems using Verilog/System Verilog.

- Define and review microarchitecture, RTL specifications, design plans, and implementation strategies.

- Drive

Clock Domain Crossing (CDC) flow

, including CDC analysis, synchronization techniques, and resolution of clock-domain-related issues.

- Work on high-speed interface designs involving

SerDes and PCIe

, including protocol-level understanding and interface integration.

- Collaborate with firmware and embedded software teams to support hardware-firmware integration, register mapping, initialization sequences, and system bring-up.

- Ensure RTL quality through lint analysis, CDC checks, synthesis readiness, timing considerations, and design reviews.

- Debug complex RTL and integration issues and drive root-cause analysis across IP and SoC levels.

- Work closely with Design Verification teams to define verification strategies,



resolve functional issues, and achieve design closure.

- Coordinate with Physical Design teams to address timing, power, area, and RTL implementation challenges.

- Mentor RTL engineers, review design deliverables, and establish coding standards and best practices.

- Own design milestones, technical deliverables, and cross-functional issue resolution.

Required Technical Skills:

- Experience:

10+ years in RTL design and SoC development, with demonstrated technical leadership experience.

- RTL Design:

Solid proficiency in Verilog/System Verilog, synthesizable RTL coding, and microarchitecture development.

- CDC Flow:

Hands-on experience with CDC analysis, synchronizer design, metastability concepts, reset-domain considerations, and CDC violation debugging.

- SerDes:

Understanding of high-speed serial interface architecture, data-path design, and SerDes subsystem integration.

- Firmware:

Understanding of hardware-firmware interaction, memory-mapped registers, interrupt mechanisms, initialization flows, and debugging during system integration.

- Design Quality:

Experience with lint, CDC tools, synthesis, timing analysis fundamentals, and RTL sign-off activities.

- Tools:

Familiarity with industry-standard EDA tools for RTL simulation, lint, CDC, synthesis, and design analysis.

📌 ASIC / RTL Design Lead (Bengaluru)
🏢 smartsoc solutions
📍 Bengaluru