At AMD, we believe technology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. SE NIOR STA SILICON DESIGN ENGINEER

Ensuring constraints quality (SDC) using industry tools like Fishtail , GCA
Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks
Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts)
Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip.
Ensuring Subsystem/full chip level Interface timing closure along DRV closure

PREFERRED EXPERIENCE:

- 4-5 years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.




- Experience with analyzing the timing reports and identifying both the design and constraints related issues.
- Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc.
- Experience in timing closure of high frequency blocks & subsystems ( Ghz range )

Good understanding of SDC constraints, OCV,AOCV,POCV analysis.

ACADEMIC CREDENTIALS:

~ Bachelors or Masters degree in computer engineering/Electrical Engineering

#AMD and its subsidiaries are equal chance, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's 'Responsible AI Policy' is available

📌 Senior Design & Analysis Engineer (India)
🏢 Xilinx
📍 India