Senior STA Engineer: You will be responsible for complete STA signoff on complex SOCs. You will work closely with RTL, IP, Architecture, Physical Design, and Verification teams to ensure robust and quality timing closure for subsystems and SOC top level.
Key Responsibilities
- Building robust understanding of the architecture
- Writing timing constraints for assigned block/subsystem/chip top.
- Timing constraints refinement along the physical design flow and active support to implementation, Floorplan and PDN teams
- Collaborate with RTL, IP, Architecture and physical design teams for timing constraints writing
- Owning complete STA closure from start of project till timing signoff.
- Timing constraints validation
- Ensure quality of STA signoff
- Building AI enabled workflows, agents etc. to improve efficiency of execution Required Skills
- Team player, Highly motivated for work and with self driven approach
- Strong expertise in STA concepts and should have worked on Functional and DFT modes.
- Hands-on experience with industry standard Timing tools
- Proficiency in Timing Constraints validation
- Proficiency in Timing ECO flows
- Good knowledge of physical design stages such as Synthesis, Placement, Clock Tree Synthesis and Routing
- Knowledge and experience of Signal integrity concepts, reports understanding and analyzing, and corrective actions
- Experience in silicon debug
- Writing Automations which helps overall STA flows
- Working experience with AI to achieve higher efficiency of execution.
- Exposure to high speed interfaces (DDR, Serdes, MIPI, USB etc)
- Exposure to AC spec timing understanding and closure Preferred Qualifications
- Past experience with Block level/Subsystem level or Top level STA
- Exposure to high-speed interfaces and IO timing.
- Strong problem-solving and communication skills. Education -Bachelor’s or Master’s in Electrical/Electronics Engineering. More information about NXP in India... #LI-29f4