Design Verification Engineer (Hyderabad)

Design Verification Engineer (Hyderabad)

22 Oct
|
Epigee
|
Hyderabad

22 Oct

Epigee

Hyderabad

Design Verification Engineer / Lead ?

Location:
Hyderabad, India – Onsite ?

Experience:
8–15 Years ? Qualification: BE / ME ? Key Skills Required: ✅ SystemVerilog & UVM ✅ SoC-Level & Subsystem Verification ✅ IP Integration & Interconnect Verification ✅ AXI, AHB & APB Protocols ✅ PCIe, Ethernet, USB, DDR, CXL, or similar high-speed interfaces ✅ Assertions, Constrained-Random Testing & Functional Coverage ✅ Simulation Debugging & Coverage Closure
• ? Interested candidates: Share your updated resume at [email protected]

📌 Design Verification Engineer (Hyderabad)
🏢 Epigee
📍 Hyderabad

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