Responsibilities:

- Perform logical packaging design (interpreting and creating netlist, ball pad layout and routing rules from customer provided information packages and schematics).
- Perform substrate layout design & stack- up analysis (parts placement, line/space routing, design rule check etc.)
- Design for feasibility / manufacturability / Cost - work with substrate suppliers, apply best industry practices to reduce cost and maximize substrate yield and meet industrial design standards such as JEDEC standards.
- Verify new internal design tools and feedback to development team and perform sign off.
- Create design documents and develop training manual.

Essential Attributes:

- Proficient in Cadence Allegro Package Designer (APD) or comparable & AutoCAD experience to design, view, edit or verify designs for optimization iterations and package sign-off.
- Working knowledge in logical net-listings, schematics usage, electrical and routing rules creation.
- Experience in designs utilizing blind, buried and micro vias would be advantageous.
- Good understanding on enabling high-density interconnects, associated mechanical, thermal and reliability issues.
- Good understanding on creating design manual, design rules, generation rules,



drawings preparation and documentation.
- Positive understanding & knowledge on Advanced Packaging architecture and semiconductor packaging process flow (Back Grinding, Dicing, Die Attach, Wire Bonding, Moulding, P&P;, Ball Attach, Trim & Form, Singulation).
- Strong presentation skills with excellent networking skills.
- Excellent English communication to work with a diverse cross-functional culture.

Qualifications:

- Bachelor or Master Degree in Electrical, Mechanical, or Materials Science Engineering.

Desired Experience Level:

- Minimum 5 to 10 years of experience in semiconductor packaging & substrate designing.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

Disclaimer: The job location mentioned in this description is based on publicly available information or company headquarters. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 IC Technology Development Lead Frame/substrate design Manager (Pune)
🏢 U3 Infotech Pte
📍 Pune