ASIC Design Verification Lead (Bengaluru)

ASIC Design Verification Lead (Bengaluru)

22 Oct
|
Einfochips
|
Bengaluru

22 Oct

Einfochips

Bengaluru

Key Responsibilities:

- Perform SoC/subsystem-level verification, including integration and verification of multiple IPs.

- Develop test plans, test scenarios, and UVM-based verification environments.

- Verify interconnects, bus protocols, and end-to-end data flows across integrated IPs.

- Debug simulation failures and drive functional coverage closure.

Required Skills:

- Robust hands-on experience in SystemVerilog and UVM.

- Experience in SoC-level verification, IP integration, and subsystem verification.

- Experience verifying multiple IPs integrated at the SoC level.

- Exposure to high-speed interfaces and protocols such as PCIe, Ethernet, USB, DDR, CXL, or other relevant protocols.

- Knowledge of on-chip protocols such as AXI, AHB, and APB.

- Experience in assertions, constrained-random testing, functional coverage, and simulation debugging.

📌 ASIC Design Verification Lead (Bengaluru)
🏢 Einfochips
📍 Bengaluru

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