23 Oct
|
Infineon Technologies
|
Bengaluru
23 Oct
Infineon Technologies
Bengaluru
Our Automotive Microcontroller R&D; team is looking for an experienced SoC High-Speed Interface Architect to join the Chip-Level Architecture team and own the chip-level integration architecture for high-speed interface PHYs on our next-generation automotive microcontroller platform. This is an SoC architecture role — not an IP design role — focused on how high-speed PHYs land on the chip, meet electrical constraints, and integrate with the platform.
Own the SoC-level integration architecture for high-speed interface PHYs (LPDDR, Ethernet PHY, HSPHY) — defining placement strategy, power delivery, reference clock assignment, and electrical compliance requirements.
Serve as the primary SoC architecture interface to PHY IP teams and external PHY vendors — driving integration feasibility assessments and resolving chip-level signal integrity issues.
Perform or oversee early signal integrity simulation and parasitic analysis for high-speed interface regions of the chip.
Maintain technical architecture documentation in compliance with ISO 26262 requirements.
Drive datasheet content for high-speed interface electrical parameters in collaboration with IP teams and customers.
Qualifications And Skills To Help You Succeed
Bachelor's or Master's degree in Electrical Engineering or related field.
At least 10 years of industry experience in semiconductor development with proven experience in high-speed interface architecture or integration.
Experience with chip-level signal integrity, jitter budgets, and eye diagram analysis for high-speed interfaces.
Understanding of PHY placement constraints, power delivery requirements, and reference clock architecture for high-speed interfaces.
Familiarity with IO ring architecture and ESD protection strategy at high-speed IO boundaries.
Fluent English required; German is a plus.
Owned chip-level integration architecture for LPDDR, Ethernet PHY, or high-speed SerDes in a previous SoC program.
Experience distinguishing SoC-level integration constraints from IP-internal design decisions — and driving the former without dictating the latter.
Contributed to datasheet electrical parameters for high-speed interface sections.
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📌 German speaking Architect (Bengaluru)
🏢 Infineon Technologies
📍 Bengaluru