Physical Design Lead ASIC / VLSI

Location: Kalyan Nagar, Bangalore
Work Mode: Hybrid
Experience: 7 10 Years
Role: Technical Lead / Physical Design Lead

1. Role Overview

We are looking for an experienced Physical Design Lead with 7 10 years of hands-on experience in ASIC Physical Design and implementation. The candidate should have solid expertise in end-to-end RTL-to-GDSII implementation, advanced technology nodes (7nm/5nm/3nm), timing closure, physical verification, and signoff. The role requires full-chip implementation and successful tapeout experience, along with 1 2 years of technical team leadership.

2. Key Responsibilities

- Lead end-to-end ASIC Physical Design implementation from floorplanning to GDSII signoff.

- Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and optimization.

- Drive Physical Design implementation at advanced technology nodes, preferably 7nm, 5nm, or 3nm.

- Execute Static Timing Analysis (STA), timing optimization, and timing closure across multiple corners and modes.

- Perform setup and hold timing analysis, constraint validation, and timing signoff.

- Manage physical verification activities, including DRC, LVS, and physical signoff.

- Perform power integrity analysis, including IR Drop and Electromigration (EM) checks.

- Work on full-chip and block-level Physical Design implementation.

- Support design integration, signoff closure, and successful ASIC tapeouts.

- Develop and maintain TCL, Python, Perl, and Make-based automation scripts.

- Lead and mentor Physical Design engineers, review implementation quality, and coordinate technical deliverables.





- Collaborate with RTL Design, DFT, STA, and Physical Verification teams to resolve implementation and signoff issues.

3. Required Qualifications
- Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related discipline.

- 7 10 years of hands-on experience in ASIC Physical Design.

- 1 2 years of team handling or technical leadership experience.

- Strong understanding of semiconductor design methodologies and RTL-to-GDSII implementation.

- Hands-on experience with advanced technology nodes, preferably 7nm/5nm/3nm.

- Demonstrated experience in full-chip implementation and successful tapeouts.

- Strong understanding of Physical Design signoff requirements and timing closure.

4. Technical Skills

Physical Design & ASIC Implementation

- RTL-to-GDSII Flow

- Floorplanning and Power Planning

- Placement and Clock Tree Synthesis (CTS)

- Routing and Physical Optimization

- Full-Chip and Block-Level Implementation

- Timing Closure and Signoff

EDA Tools

- Place & Route: Synopsys ICC2 / Fusion Compiler or Cadence Innovus

- Static Timing Analysis: Synopsys Prime Time or Cadence Tempus

- Physical Verification: Siemens Calibre / Synopsys ICV / Cadence Pegasus

- Power Integrity: Ansys Red Hawk or Cadence Voltus

Timing, Power & Signoff

- Static Timing Analysis (STA)

- Multi-Mode Multi-Corner (MMMC) Analysis

- Setup and Hold Timing Closure

- DRC / LVS

- IR Drop / Electromigration (EM) Analysis

- Physical Signoff and Tapeout

Scripting & Automation

- TCL

- Python

- Perl

- Make / Makefile

Technology Nodes

- Advanced CMOS Technology Nodes

- 7nm / 5nm / 3nm preferred

#LI-SD1

📌 Physical Design Lead – ASIC / VLSI (India)
🏢 Best NanoTech
📍 India