About the Role

We are looking for passionate and skilled Design Verification Engineers to join our growing semiconductor engineering team. If you have hands-on experience in functional verification and a strong understanding of digital design concepts, we would love to connect with you!

Key Responsibilities

- Develop and maintain testbenches using SystemVerilog and UVM.
- Understand design specifications and develop comprehensive verification plans.
- Write, debug, and optimize test cases and sequences.
- Perform functional verification, simulation, and regression testing.
- Analyze functional and code coverage, identify gaps, and drive coverage closure.
- Debug simulation failures and work closely with RTL design teams to resolve issues.
- Contribute to verification sign-off and quality deliverables.

Required Skills

- Strong knowledge of Digital Design and Verilog/SystemVerilog.
- Hands-on experience with UVM-based verification.
- Understanding of constrained-random verification,



assertions (SVA), and functional coverage.
- Experience with simulation and debugging tools such as VCS, Questa, or Xcelium.
- Good knowledge of testbench development, debugging, and verification methodologies.
- Strong problem-solving and analytical skills.

Experience Levels

- 1–3 Years: Robust fundamentals in SystemVerilog, UVM, testbench development, and debugging.
- 3–5 Years: Independent ownership of verification components, test planning, coverage analysis, and debug.
- 5–7 Years: Expertise in verification architecture, complex IP/subsystem verification, coverage closure, and mentoring junior engineers.

Why Join Us?

Be part of a growing semiconductor engineering team, work on challenging VLSI projects, and build your expertise in next-generation chip design and verification.

📌 Design Verification Engineer (Bengaluru)
🏢 Talentrabbit
📍 Bengaluru