Position Title: Design Verification Engineer
Location: Hyderabad or Bengaluru
Work Mode: Onsite/Hybrid
Experience: 5+ years
Skills Required
- Robust expertise in SystemVerilog, UVM and Verilog/VHDL
- Testbench development, OOP concepts, randomization, constraints and SVA
- UVM components, RAL, sequences, virtual sequences and reusable verification environments
- Functional coverage, cross coverage, coverage analysis and closure
- Assertion-based verification and debugging of design and simulation issues
- Hands-on experience with at least one PHY protocol: DDR/LPDDR PHY, PCIe PHY, USB PHY, MIPI D-PHY/C-PHY, Ethernet PHY, SerDes PHY or UFS PHY
If interested, Please share your profile to
[email protected]
📌 . Design Verification Engineer – Functional Verification (Bengaluru)
🏢 3iTech Global
📍 Bengaluru