- The candidate is expected to have a transparent understanding of BSCAN, MBIST, SCAN, ATPG, and Simulation concepts.
- Must be hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using industry-standard tools of Cadence/Siemens Tessent/Synopsys.
- Candidate must have worked on zero delay as well as SDF Timing Simulations
- Must have good debugging skills using GUI mode of industry standard simulators like VCS, NCSim or Xcelium.
- The candidate should have worked on fault models like stuck-at, Transition Delay Faults(TDF),
IDDQ and should have experience in scan test coverage improvement techniques.
- The candidate should have worked in SoC-level DFT with experience in OCC/OPCG insertion, EDT/Compression logic insertion, clock module handling for scan purposes and post-silicon bring-up and /or production activities with exposure to Tester debug usings shmoo plots and graphs.
- The candidate should have experience of providing test mode timing constraints to STA and PD teams.
- Additional knowledge of perl/tcl scripting will be an advantage.
- Good communication skills and debugging skills are a must to have qualities for this role as it involves cross-functional teams and customer teams communications along with internal DFT team leading and mentoring of DFT Engineers.