Experience:
4-6 Years (Minimum 4 Years) We are looking for experienced Design Verification (DV) Engineers with expertise in DFT-related Verification to join our team.
Key Responsibilities
✅ Support RTL and Gate-Level Simulation (GLS) verification of DFT features in SoC functional mode. ✅ Validate DFT features that are part of the SoC power-up sequence, including:
• DFT IST
• SRAM Repair
• MBIST
• JTAG ✅ Collaborate with cross-functional teams to ensure robust verification and seamless silicon bring-up. Required
Skills:
✔ Robust experience in SoC Design Verification ✔ Hands-on expertise in DFT Verification ✔ RTL Verification and Gate-Level Simulation (GLS) ✔ Knowledge of MBIST, JTAG, SRAM Repair, and DFT IST ✔ Experience with SystemVerilog/UVM-based verification environments ✔ Strong debugging and problem-solving skills
📌 DV Engineers (Bengaluru)
🏢 QTIMINDS
📍 Bengaluru
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