AMS Design & Analog Layout Engineer | Semiconductor/VLSI | HCLTech

Join HCLTech’s semiconductor engineering team and work on challenging Analog and Mixed-Signal (AMS) IC design and analog layout across advanced semiconductor technologies.

In this role, you will contribute to the design, implementation, verification, and silicon validation of high-performance analog/mixed-signal blocks. You will collaborate with circuit designers, layout engineers, verification teams, and other cross-functional stakeholders to deliver robust, silicon-ready solutions for global semiconductor programs.

Key Responsibilities:

- Design, simulate, and validate analog and mixed-signal circuits at transistor/block level.
- Develop high-quality custom analog layouts aligned with circuit specifications, PPA targets, and foundry requirements.
- Perform pre-layout and post-layout simulations and analyze performance across PVT conditions.
- Implement critical analog layout techniques including matching, symmetry, common-centroid placement, shielding, guard rings, parasitic-aware routing, and noise isolation.
- Perform and resolve DRC, LVS, ERC, and parasitic extraction (PEX) issues to achieve clean layout closure.
- Work closely with circuit design and layout teams on layout-dependent effects, parasitic impact, matching, signal integrity, and performance optimization.
- Support AMS block integration, verification, debugging, and design reviews.
- Contribute to silicon bring-up, characterization, validation, and post-silicon debugging, where applicable.
- Prepare technical documentation and actively participate in design/layout reviews.
- Drive improvements in design methodologies, automation, quality, and overall design efficiency.

Required Skills & Experience:

- Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, VLSI, Microelectronics, or a related discipline.




- 3+ years of relevant experience in Analog/Mixed-Signal IC Design, Analog Layout, or closely related semiconductor development.
- Strong knowledge of CMOS fundamentals, semiconductor device physics, analog circuit concepts, and IC design/layout methodologies.
- Hands-on experience with industry-standard EDA environments such as Cadence Virtuoso and relevant Synopsys/Siemens EDA tools.
- Experience with DRC, LVS, ERC, PEX and post-layout verification.
- Positive understanding of process variations, device matching, parasitics, noise, reliability, and layout-dependent effects.
- Ability to debug complex circuit/layout issues and collaborate effectively across design, verification, and physical implementation teams.
- Strong analytical, problem-solving, documentation, and communication skills.

Preferred / Nice-to-Have Skills:

- Experience working on high-speed, low-power, or precision analog/mixed-signal circuits.
- Exposure to blocks such as PLL, DLL, ADC, DAC, LDO, Bandgap, Op-Amp, Comparator, SerDes/PHY, Clocking, or Data Converter circuits.
- Experience with FinFET or advanced semiconductor process nodes, depending on the program.
- Experience in full-custom analog layout and physical verification flows.
- Exposure to semiconductor products for automotive, communications, computing, consumer, or IoT applications.
- Experience working with geographically distributed semiconductor design teams.
- What Makes This Opportunity Exciting

At HCLTech, you’ll have the opportunity to contribute to complex semiconductor engineering programs, collaborate with global engineering teams, and work across the IC development lifecycle, from design and layout through verification and silicon validation.

If you are passionate about Analog/Mixed-Signal IC Design or Analog Layout and enjoy solving complex silicon-level engineering challenges, we would love to connect with you.

📌 Analog Layout Engineer (Bengaluru)
🏢 HCLTech
📍 Bengaluru