The RTL Design Engineer role turns architecture specifications into clean, synthesizable SystemVerilog that other engineers can verify and implement.

As a fresher you will start with well-bounded blocks such as FIFOs, arbiters and AXI interface logic, then grow towards larger units under the guidance of senior engineers.

What you will work on

- Write synthesizable SystemVerilog for blocks defined in the specification
- Follow coding and lint rules; fix lint, CDC and reset-related findings
- Work with verification engineers to resolve failures and clarify intent
- Check area and timing effects of your design choices with synthesis feedback
- Document interfaces, parameters and assumptions for every block
- Take part in design reviews and incorporate feedback

Skills Required And How Deep Depth shows how far along you should be on day one. We teach the rest.

- SystemVerilog RTL codingStrong

Core daily activity; code must be synthesizable and readable
- Digital design: FSMs, FIFOs, arbitersStrong

These are the building blocks of nearly every interface
- Clocking, reset and basic CDC awarenessWorking knowledge





Common source of silicon bugs; you must know the risks
- Bus protocols (AXI4 basics)Working knowledge

The NX-AXI DMA engine uses AXI4 and AXI4-Lite
- Simulation and waveform debugStrong

You prove your own RTL works before handing it over

Nice to have

- Lint tool experience
- Synthesis and timing report reading
- A completed RTL project in a public repository

Tools you will use
- SystemVerilog
- Verilator or commercial simulators
- Lint tools
- Synthesis tools
- Git and Make

What you will learn
- Writing RTL that synthesizes the way you expect
- Reading timing reports and fixing critical paths
- Collaborating with verification on specification gaps

Your first 90 days
- First 30 daysComplete a reference block with testbench and lint-clean code.
- Days 31 to 60Deliver an interface block with documentation and review.
- Days 61 to 90Own a block through verification sign-off for that block.

Who fits: You care about the quality of every line of code because you know someone will debug it at 2 a.m.

📌 RTL Design Engineer (Bengaluru)
🏢 DECCANX
📍 Bengaluru