Role: Senior Design Verification Engineer – Ethernet (ASIC / SoC)

Location:
Hyderabad / Bengaluru, India

Experience:
7+ Years Domain: Ethernet / Networking / ASIC / SoC Verification Employment Type: Full-Time Role Overview: We are seeking an experienced Design Verification Engineer (7+ Years) to lead and drive the functional verification of high-speed Ethernet IPs and networking SoCs. In this role, you will be responsible for architecting scalable, reusable SystemVerilog/UVM testbenches, verifying complex packet processing units, and ensuring complete protocol compliance for next-generation networking hardware.

Key Responsibilities

- Testbench Architecture & Development: Design, build, and maintain constrained-random verification environments and reusable testbenches using SystemVerilog and UVM for Ethernet IPs, Subsystems, and full SoCs.
- Protocol & Module Verification: Execute detailed verification of Ethernet MAC, PCS, PMA , and packet-processing pipelines against IEEE standards and design specifications.
- Verification Planning: Formulate comprehensive verification plans, feature extraction, test scenarios, and assertion coverage strategies based on architectural specifications.
- Assertions & Coverage Closure: Implement SystemVerilog Assertions (SVA), define functional coverage models, analyze code/line coverage, and drive 100% coverage closure.
- Regression & Debugging: Setup and manage automated regression suites, perform root-cause analysis on complex failure logs, and work closely with RTL designers to resolve hardware bugs.
- Technical Mentorship:



Mentor junior verification engineers and participate in architectural reviews and design-verification sign-offs. Required Qualifications & Technical

Skills:

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Experience:
Minimum 7+ years of hands-on experience in ASIC/SoC Design Verification.
- Ethernet & Networking Expertise: Deep domain knowledge in networking protocols, packet processing architectures, and hands-on experience verifying Ethernet MAC/PCS/PHY layers.
- HDL & Methodologies: Advanced mastery of SystemVerilog and UVM (Universal Verification Methodology).
- Constrained-Random Verification: Strong capability in developing constrained-random test cases, virtual sequencers, scoreboards, drivers, and monitors.
- Formal & Assertions: Proficiency in writing SystemVerilog Assertions (SVA) and building functional coverage models.
- Scripting & Automation: Solid scripting expertise in Python, Perl, or Tcl for regression automation, test creation, and tool flows.
- Tools: Hands-on expertise with industry-standard EDA simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium/Verdi, Siemens Questa). Preferred

Qualifications:

- Experience with high-speed Ethernet standards ( 10G, 25G, 100G, 400G, or 800G / IEEE 802.3 specs).
- Exposure to SerDes / PHY interfaces (XGMII, XLGMII, 25GMII, 50GMII) and PCIe/AXI bus protocols.
- Experience with Hardware Emulation (Palladium, Zebu) or FPGA Prototyping for high-speed networking IP validation.
- Familiarity with VIPs (Verification IP) integration and multi-layer protocol analyzers.

Education:

- Bachelor’s or Master’s Degree in Electronics & Communication Engineering (ECE), Electrical & Electronics Engineering (EEE), Computer Engineering, or a closely related discipline.

📌 Senior Design Verification Engineer (Bangalore Metropolitan Area)
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📍 Bangalore Metropolitan Area