01 Nov
|
Pqangels Technologies
|
Bengaluru
01 Nov
Pqangels Technologies
Bengaluru
Job Description
Develop verification settings using SystemVerilog/UVM
Create test plans, testcases, assertions, and coverage models
Debug RTL and verification issues
Work closely with RTL designers and architects
Perform regression and coverage closure
Responsibilities
IP/SoC level verification
Functional and code coverage analysis
Constraint random verification
Protocol verification (PCIe,USB,DDR,HBM, AXI, APB, SPI, I2C, etc.)
Automation and scripting support
Required Skills
Solid SystemVerilog and UVM knowledge
Experience in ASIC/SoC verification flow
Debugging skills using simulators
Perl/Python/Shell scripting knowledge preferred
This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
📌 Dv Engineer Systemverilog & Uvm Verification Pq Angels Bengaluru
🏢 Pqangels Technologies
📍 Bengaluru