Job Summary

- Design memory layouts for various building blocks including:
- Bit cell array
- Row decoder
- Column decoder
- Sense amplifiers
- Input/Output (I/O) blocks
- Integrate top-level memory blocks
- Perform physical verification using tools like Design Rule Check (DRC) and Layout Versus Schematic (LVS)
- Ensure layouts meet Design for Manufacturability (DFM) and Design for Yield (DFY) requirements
- Analyze layouts for potential power and signal integrity issues
- May involve scripting using languages like PERL, Shell, TCL, or Skill

Key Responsibilities

- Lead the design and development of memory layouts for complex ICs, including:
- High-density SRAM and DRAM memories
- Specialty memory blocks (e.g., ROM, CAM)
- Define memory architecture and sub-block specifications
- Develop and implement advanced layout techniques for low-power, high-speed memory design




- Collaborate with design, logic, and verification teams to ensure seamless integration
- Mentor junior engineers and provide technical guidance
- Stay up-to-date on the latest memory design trends and technologies
- Perform comprehensive physical verification using DRC, LVS, and other tools
- Drive Design for Manufacturability (DFM) and Design for Yield (DFY) initiatives
- Analyze layouts for potential power integrity and signal integrity issues
- May involve scripting automation for layout tasks using languages like PERL, Shell, TCL, or Skill

Skill Requirements

Must Have Skill

AMS Design

Valuable to Have Skill

Other Requirements

📌 Senior Designer (Chennekothapalli)
🏢 HCLTech
📍 Chennekothapalli