Role SummaryOwn the integration layer between Linux user space, programmable logic, and radio control software for a UHD-based platform with Mavenir-style processing split. This engineer will bridge Yocto build systems, XSA-to-DTSI hardware description flow, UIO/register access, and RTL device integration for production-grade radio subsystem control.

Key Responsibilities

Build and maintain Yocto layers/recipes for UHD-based images and integration components. Integrate FPGA hardware exports (XSA) into Linux device-tree flows (DTS/DTSI), including address maps, interrupts, clocks, and memory regions.

- Implement and validate RTL device exposure to software (UIO, kernel interfaces, register maps, driver hooks as needed).
- Develop/maintain C++ integration code in UHD-adjacent control paths for register access, device discovery, and diagnostics.
- Align software control flow with Mavenir-style PS integration patterns (process orchestration, CLI/tool-driven configuration, control plane interaction).
- Debug end-to-end data/control path issues across FPGA, boot flow, Linux, and user-space applications.
- Produce integration documentation, bring-up checklists, and reproducible test workflows for CI/lab use.

Job Requirements





1.5+ years in embedded Linux and SoC/FPGA system integration.

2. Solid Yocto/Open Embedded experience:

- custom layers, bbappend, image recipes, dependency management, reproducible builds.

3. Device tree proficiency:

- XSA to DTSI workflows, node binding, address translation, interrupt wiring, overlay/debug.

4.FPGA-software interface experience:

- MMIO/register maps, UIO/devmem/debug tooling, AXI-based peripheral integration.

5.C/C++ systems programming on Linux (cross-compiled targets).
6. Practical board bring-up and lab debugging skills:

- serial console, bootloader/kernel logs, oscilloscope/logic analyzer familiarity.

7. Version control and release hygiene (Git, review discipline, traceable change logs).

Nice-to-Have

- Prior UHD/USRP or SDR stack integration.
- O-RAN RU stack familiarity, including split architecture and control/management workflows.
- RFNoC awareness (for comparison/migration context even if not used in active path).
- CI/CD for embedded platforms (artifact caching, sstate strategy, hardware-in-loop tests).
- Experience with performance profiling and latency tuning across PS-PL boundaries.

📌 Platform Development Engineer (India)
🏢 Mavenir
📍 India