Job Title: Engineering - Verification Engineer

Location: Hyderabad

Duration: 12 Months Contract

Experience: 3+

Job Overview

Looking for skilled Design Verification Engineers with 3+ years of experience in functional verification of digital designs. Candidates should have robust knowledge of System Verilog and fundamental verification concepts, along with hands-on experience in developing testbenches, writing test scenarios, debugging simulation failures, and verifying complex digital designs.

Key Responsibilities

- Develop and execute functional verification testbenches using System Verilog and UVM.
- Understand design specifications and develop verification plans, test scenarios, and test cases.
- Write directed and constrained-random tests to verify design functionality and corner cases.
- Develop and maintain testbench components, checkers, and scoreboards.
- Write System Verilog Assertions (SVA) to verify design behavior and protocol requirements.
- Develop functional coverage models and analyze coverage results to identify verification gaps.
- Debug simulation failures using waveforms, logs, and simulation tools.




- Collaborate with RTL design and verification teams to resolve functional issues.
- Execute regression tests and contribute to verification quality and coverage closure.

Mandatory Skills

- 3+ years of hands-on experience in Design Verification.
- Strong knowledge of System Verilog programming.
- Good understanding of functional verification concepts and methodologies.
- Experience with constrained-random verification and functional coverage.
- Knowledge of System Verilog Assertions (SVA).
- Understanding of digital design fundamentals, including FSMs, FIFOs, counters, and arbiters.
- Experience using simulation and debugging tools such as VCS, Xcelium, or Questa.
- Good analytical, debugging, and problem-solving skills.

Preferred Skills

- Hands-on experience with UVM methodology.
- Knowledge of AMBA protocols such as AXI, AHB, or APB.
- Experience with scripting languages such as Python, Perl, or Shell.
- Exposure to IP-level or SoC-level verification.
- Familiarity with regression management and verification coverage closure.

📌 Design Verification Engineer (India)
🏢 Sunrisesys
📍 India