LEC Engineer (Logical Equivalence Checking) Company: SmartSoC Solutions Pvt. Ltd. Role: LEC Engineer / Formal Verification Engineer

Location:
Bangalore, India

Experience:
5–10 years (versatile based on project requirements) Job Summary We are looking for a skilled LEC Engineer with hands-on experience in Logical Equivalence Checking using Cadence Conformal. The candidate will be responsible for setting up LEC flows, performing equivalence checks, debugging mismatches, and ensuring logical consistency between RTL and synthesized netlists.

Key Responsibilities
• Set up, configure, and execute Logical Equivalence Checking (LEC) flows using Cadence Conformal.
• Perform RTL-to-gate-level and gate-to-gate equivalence checking.
• Debug and resolve equivalence failures, mismatches, and non-equivalent compare points.
• Analyze RTL, synthesized netlists, and formal verification reports.
• Configure tool settings, constraints, libraries, and design setup files.
• Identify and resolve issues related to synthesis transformations, naming mismatches, and design optimizations.
• Collaborate with RTL design, synthesis, and physical design teams to resolve functional equivalence issues.




• Automate and improve LEC flows using scripting languages such as Tcl, Perl, or Python.
• Ensure successful LEC sign-off for block-level and/or full-chip designs. Required Skills
• Hands-on experience with Cadence Conformal for Logical Equivalence Checking.
• Strong experience in LEC flow setup, configuration, execution, and debugging.
• Knowledge of RTL-to-netlist and gate-to-gate equivalence verification.
• Understanding of Verilog/SystemVerilog and synthesized netlists.
• Familiarity with synthesis concepts, including logic optimization, retiming, and design transformations.
• Ability to analyze LEC reports and troubleshoot equivalence failures.
• Scripting knowledge in Tcl, Perl, or Python. Preferred Qualifications
• Experience with formal verification methodologies and semiconductor ASIC/SoC design flows.
• Exposure to synthesis tools and RTL design/debugging.
• Understanding of low-power design techniques, scan insertion, and DFT-related transformations.
• Experience in block-level or full-chip LEC sign-off. Education Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related field.

📌 RTL LEC Engineer (Bengaluru)
🏢 smartsoc solutions
📍 Bengaluru