03 Nov
|
Leadsoc Technologies
|
Bengaluru
03 Nov
Leadsoc Technologies
Bengaluru
Lead Physical Design Engineer
Location:
Bengaluru
Experience:
6–12 Years Role Overview We are looking for a technically strong Lead Physical Design Engineer with hands-on expertise in full-chip physical implementation, PPA optimization, EM/IR analysis, and signoff closure. The ideal candidate should have solid ownership of end-to-end physical design execution, from floorplanning to final signoff, across advanced technology nodes.
Key Responsibilities
• Drive end-to-end Full-Chip Physical Design implementation from floorplanning to tapeout.
• Own floorplanning, power planning, placement, CTS, routing, and physical optimization.
• Perform EM/IR analysis and closure, including power integrity and reliability checks.
• Drive timing closure, congestion optimization, and PPA improvements.
• Execute physical verification and signoff activities, ensuring design readiness for tapeout.
• Work extensively on timing, signal integrity, DRC, LVS, and antenna closure.
• Debug complex physical design issues and drive critical path optimization.
• Collaborate with RTL, DFT, STA, methodology,
and technology teams for full-chip integration.
• Drive signoff quality, implementation efficiency, and design convergence. Required Technical Skills
• 6–12 years of hands-on experience in ASIC Physical Design.
• Strong expertise in Full-Chip Physical Design and Implementation.
• Proficiency in Cadence Innovus for physical implementation.
• Strong hands-on experience in EM/IR analysis and closure.
• Experience with physical design signoff methodologies and tapeout readiness.
• Strong understanding of STA, timing closure, clock tree synthesis, routing, and physical verification.
• Experience with industry-standard EDA tools and advanced technology nodes.
• Strong debugging, optimization, and problem-solving capabilities. Preferred Expertise
• Experience in advanced-node SoC implementation.
• Exposure to high-performance, low-power design methodologies.
• Experience driving full-chip PPA and signoff closure independently.
📌 Lead Physical Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru