Job Requisition: Mid-Level SoC Design Engineer (ARM Architecture & Corestone Experience)

Location:
Hyderabad, India Department: Hardware Engineering – SoC Design Employment Type: Full-Time About Azimuth AI Azimuth AI is building next-generation AI compute platforms and silicon that deliver breakthrough performance, efficiency, and scalability. Our cross-functional hardware, software, and silicon teams collaborate closely to push the boundaries of edge and cloud AI acceleration. We are expanding our SoC Architecture & Design team in Hyderabad to support our rapidly growing AI silicon roadmap. Role Overview We are seeking a Mid-Level SoC Design Engineer with robust expertise in ARM architecture and hands-on experience working with Arm Corestone reference systems. The role involves supporting subsystem design, integration, and optimization activities across Azimuth AI’s next-generation SoCs. In addition, we are looking for engineers with a solid background in ASIC SoC and RTL design, with an emphasis on front-end ASIC design techniques and methodologies. You will collaborate with architecture, verification, and physical design teams to bring complex ARM-based subsystems to production-quality readiness.

Key Responsibilities
• Design and integrate ARM-based subsystems derived from Arm Corestone reference packages into Azimuth AI SoCs.
• Implement and modify RTL for CPU subsystems, AMBA interconnects, memory controllers, and peripheral IP.
• Collaborate with architecture teams on feature definition, microarchitecture updates, and performance targets.
• Work closely with verification teams to debug functional issues and ensure high-quality coverage closure.
• Support synthesis, timing analysis, and physical design teams during SoC execution.
• Drive documentation, design reviews,



and bring-up support for early silicon and emulation platforms.
• Contribute to methodology improvements for subsystem integration and design scalability. Required Qualifications
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 4+ years of experience in SoC or subsystem design.
• Strong knowledge of ARM architecture, AMBA protocols (AXI, AHB, APB), and system-level integration.
• Hands-on experience with Arm Corestone-based packages or similar ARM reference designs.
• Solid experience in ASIC front-end design, including RTL development and integration flows.
• Experience in ASIC synthesis, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) techniques using Cadence Tools.
• Proficiency in Static Timing Analysis using Cadence tools.
• Familiarity with low-power design techniques, UPF, and cadence low power tools (a plus).
• FPGA prototyping experience is desirable.
• Strong debugging skills across simulation, lint, CDC, and synthesis environments.
• Ability to collaborate in a fast-paced, cross-functional engineering environment. Preferred Qualifications
• Knowledge of low-power design techniques and clock/power domain architecture.
• Exposure to AI/ML accelerator-based SoCs is a plus.
• Familiarity with FPGA prototyping, emulation platforms, or early silicon bring-up.
• Advanced degrees (B.
Tech/M.
Tech/BE/ME/M.
Sc/M.
S) in Computer Science or Electronics/Electrical Engineering. Why Join Azimuth AI
• Work on cutting-edge silicon shaping the future of AI compute.
• Collaborate with top-tier engineers in architecture, design, algorithms, and systems.
• Opportunity to influence and architect foundational technologies in our AI SoC roadmap.
• Competitive compensation, benefits, and rapid career growth.

📌 System-on-Chip Design Engineer (Hyderabad)
🏢 Azimuth AI
📍 Hyderabad