Job Description
LeadIC Design is hiring | Analog Layout Engineer We are looking for experienced Analog Layout Engineers with strong hands-on expertise in advanced FinFET technology nodes.
Experience:
4+ Years Key Requirements
• 4+ years of hands-on Analog Layout Design experience.
• Strong experience in FinFET technology.
• Hands-on exposure to TSMC 3nm, 5nm or 7nm process nodes.
• Proficiency in Cadence Virtuoso.
• Robust knowledge of DRC, LVS and physical verification.
• Expertise in matching, symmetry, parasitic-aware layout and analog layout techniques.
• Preferred Skills
• Advanced CMOS process technologies.
• Analog and mixed-signal custom layout.
• Post-layout verification and debugging.
Location:
Bengaluru, Hyderabad, Pune Interested candidates are encouraged to apply directly through LinkedIn.
📌 Analog Layout Engineer (Bengaluru)
🏢 leadIC Design
📍 Bengaluru
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