Hi All, Greetings from HCL Tech. We are Hiring: Senior VLSI RTL Design Engineer. Locations: Bengaluru, Noida, Chennai & Hyderabad. Min 4 to 15+ Years of Experience. Job Summary: We are looking for an RTL IP-Level Design Engineer responsible for designing, integrating, and ensuring the quality of RTL IPs through comprehensive static and functional quality checks. The role involves ownership of RTL from development through quality signoff prior to backend handoff.

Key Responsibilities
RTL Design & IP Development:
· Develop synthesizable RTL (Verilog / SystemVerilog) for IP blocks and subsystems based on micro-architecture specifications.
· Implement clean, scalable, and reusable IP RTL following coding guidelines and industry best practices.
· Design and maintain wrappers, parameterized RTL, and configuration logic. IP Integration & SoC Readiness
· Integrate IPs into subsystem / SoC-level hierarchies.
· Ensure correct clock, reset, power, and interface connectivity.




· Support AMBA-based interfaces (AXI/APB/AHB) and peripheral protocols (SPI, I2C, UART). RTL Quality Checks & Signoff – Lint /CDC / RDC analysis Required Skills &

Qualifications:
Technical

Skills:
· HDLs: Verilog, SystemVerilog.
· RTL Quality Tools: SpyGlass Lint / CDC / RDC.
· Questa CDC, VC-RDC (or equivalent).
· Simulation & Debug: VCS / Questa / Xcelium / Verdi / DVE. Programming/Scripting:
· Proficiency in Python/Perl/Shell scripting for automation.

Education:
· B.
Tech / M.
Tech in Electronics / Electrical / Computer Engineering or equivalent. Soft

Skills:
· Strong analytical and debugging skills.
· Valuable communication and cross-functional collaboration. Interested Engineers ping me or send invitation to connect further. Email I'd: [email protected] Mobile: +91 (phone hidden).

📌 Senior VLSI RTL Design Engineer (Bengaluru)
🏢 HCLTech
📍 Bengaluru