Company Description 7Rays Semiconductors delivers end-to-end VLSI design solutions that enable clients to achieve execution excellence across complex semiconductor projects. The company’s expert team specializes in architecture, RTL design, design verification, validation, DFT, physical design implementation, and post-silicon validation. Using modern technologies and methodologies, 7Rays supports customers through the full chip development lifecycle. Team members work on challenging, cutting-edge projects in a collaborative, engineering-focused environment. Role Description The Senior Design Verification Engineer will lead verification activities for complex digital designs, ensuring functional correctness, performance, and robustness. This is a full-time, on-site role based in the Greater Bengaluru Area, working closely with RTL, architecture, and validation teams. Day-to-day responsibilities include developing verification plans, creating and maintaining testbenches, writing and reviewing test cases, and executing simulation and formal verification workflows. The role involves analyzing coverage, performing root-cause debugging of functional and performance issues, and driving closure on verification milestones. The engineer will also contribute to methodology improvements, mentor junior team members,



and collaborate with cross-functional stakeholders to deliver high-quality silicon on schedule. 7Rays Semiconductors is hiring experienced DFT (Design for Testability) Engineers for our Bangalore location.

Experience:
4+ Years

Location:
Bangalore Key Skills Required:
• Hands-on experience in DFT implementation and methodology.
• Solid experience in Scan Insertion and Boundary Scan (JTAG).
• Good knowledge of MBIST, ATPG, and Scan Compression.
• Experience in ATPG pattern generation and fault simulation.
• Knowledge of Stuck-at and Transition Delay Fault (TDF) models.
• Experience in DFT verification, simulation, debugging, and coverage analysis.
• Exposure to OCC/OPCG, EDT, and SoC-level DFT.
• Working knowledge of Synopsys, Siemens Tessent, or Cadence DFT tools.
• Experience with VCS, NCSim, or Xcelium simulators.
• Knowledge of Perl/TCL/Python scripting will be an added advantage. If you are interested in this opportunity, please share your updated resume. Feel free to share this opportunity with your professional network. Regards, Balachowdaiah P. TA Manager | 7Rays Semiconductors Mobile: (phone hidden) Email: [email protected]

📌 Senior Design Verification Engineer (Bengaluru)
🏢 7rays Semiconductors
📍 Bengaluru