03 Nov
|
UANDWE
|
Bengaluru
Job Description
Location:
Bangalore, India Job
Responsibilities:
• Layout Design of SRAM/CAM/RF compiler memories in 5/3FF technology.
• Development of key building blocks of memory architecture such as Row Decoder, IO, Control.
• Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing.
• Compiler level integration, verification of Compiler/Custom memories.
Skills:
• Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc.
• Good problem solving and logical reasoning skills.
• Valuable communication skills required.
📌 Memory Layout Design Engineer (Bengaluru)
🏢 UANDWE
📍 Bengaluru