We are pleased to reach out to you regarding a potential opportunity for the position of Lead Engineer. Tessolve Semiconductors a venture of Hero Electronix, part of $5B Hero Group companies a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions. Currently we are 2300+ employees worldwide. We are Global Multi
- National Company having Engineering and Sales presences in India, Malaysia, Singapore, USA, UK, Europe, and China. Tessolve has strategic and sustainable growth plan to ensure the business stability to our valued customers and to protect the career of our employees even under disturbed Business situations. Position: Lead Engineer

Location:
Bangalore Experience Required: 8+ yrs Work Mode: In office

Job Description
Lead and execute Memory Subsystem and LPDDR validation activities across post-silicon environments.
• Develop validation strategies, test plans, test cases and coverage plans for memory controllers, PHY and LPDDR interfaces.
• Perform LPDDR4/LPDDR4X/LPDDR5/LPDDR5X interface validation, including initialization, training, timing and functional testing.
• Validate different memory configurations, frequencies, data rates, channels, ranks and memory densities.
• Debug memory-related failures at SoC, controller, PHY, firmware and board level.
• Work closely with hardware design teams to understand memory controller, PHY, clocking, reset, power and interface architecture.
• Review hardware design specifications, block diagrams, schematics and relevant design documentation.
• Support silicon bring-up, memory initialization and platform-level validation.
• Develop and maintain automation scripts for validation, debug and data collection using Python,



Shell or similar scripting languages.
• Validate memory reliability, stability and performance under different system workloads.
• Mentor junior engineers and provide technical guidance to the validation team.
• Lead technical discussions with internal teams and customers and communicate project status, risks and dependencies. Key

Skills:
Memory subsystem and LPDDR validation, Silicon bring-up, Hardware-level debug. Hardware design understanding, Validation strategy and test planning, Validation automation

Experience:
Strong experience in Memory Subsystem validation and debug.
• Hands-on experience with LPDDR4/LPDDR4X/LPDDR5/LPDDR5X
• Good understanding of Memory Controller architecture, DDR/LPDDR PHY, Read/write leveling, Memory channels, ranks and banks, ECC and memory error handling.
• Strong knowledge of post-silicon validation and silicon bring-up.
• Experience in debugging failures across hardware, firmware and software layers.
• Ability to read and understand schematics, block diagrams and hardware specifications
• Good understanding of system-level interfaces such as PCIe, USB, I2C, SPI, UART, JTAG, etc., is an added advantage.
• Understanding SoC and memory subsystem architecture.
• Understanding memory controller and PHY integration
• Reading and analyzing schematics and board layouts.
• Lead a team of validation engineers and own technical deliverables.
• Define validation priorities, execution plans and debug strategy and Review test plans, test cases, automation and debug reports.
• Mentor team members on memory validation and hardware debug methodologies.
• Good Communication and interpersonal skills Best Regards, Shyam Sheriel S | Lead
- Talent Acquisition Shyam.
[email protected] Tessolve Semiconductor Pvt Ltd E-City Bangalore, India www.tessolve.com

📌 Lead Engineer (Bengaluru)
🏢 TESSOLVE
📍 Bengaluru