**We are looking for an experienced SoC DFT Lead to join NXP at our Pune location.

Experience: 13-17 Years The ideal candidate should have deep expertise across the complete DFT lifecycle, from DFT architecture definition through silicon bring-up, validation, and customer-return analysis, for large and complex SoCs. Experience leading DFT execution across multiple successful tape-outs is highly preferred.

Key Requirements**

✅ **Solid understanding of DFT Architecture for complex SoCs, including:

Multiple

DFT partitionsMulti-clo ck-domain designsMulti-pow er-domain architecturesLow-power

DFT methodologies

✅ Hands-on expertise in DFT implementation at the RTL level< /p>

✅ **Strong knowledge of Scan Architecture and ATPG, including:

Scan inse rtion and implementationTest time optimizationCompressi on methodologiesEfficient

ATPG strategiesExposure to SSN (Streaming Scan Network) is a plus

✅ **Extensive experience in MBIST architecture, implementation, and verification, including:





Memories with repair capabilityMemories without repair capabilityMemory re pair analysis and sign-off flows

✅ Experience with Boundary Scan (BSCAN/JTAG) implementation and verification< /p>

✅ **Good understanding of:

Siliconb ring-up and debugDevice ch aracterizationPost-sili con validation

✅ **Strong knowledge of test cost and test time optimization techniques

Preferred

Profile

Proven t r ack record of leading DFT execution for large-scale SoCsExperienc e managing DFT activities across multiple successful tape-outsAbility t o drive DFT planning, execution, sign-off, and post-silicon debug independentlyStrong co llaboration skills with Design, Verification, Physical Design, Product Engineering, and Test Engineering teams

? If you match the above requirements and are interested in exploring this opportunity, please DM me with your updated profile/resume.****

📌 SoC DFT lead (Pune)
🏢 NXP Semiconductors
📍 Pune