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???????? is a global leader in wireless communications, multimedia, and AI‑driven semiconductor solutions. With a portfolio that powers smartphones, smart‑home devices, automotive infotainment, and IoT ecosystems, MediaTek delivers cutting‑edge system‑on‑chip (SoC) technologies to more than 2 billion devices worldwide. Our R&D; centers — including the flagship Hsinchu campus — bring together world‑class engineers who design industry‑defining chips on advanced process nodes (2 nm – 6 nm).

We are expanding our physical‑design team to accelerate the next generation of high‑performance, power‑efficient products. If you thrive in a fast‑paced, innovative environment and enjoy leading large‑scale block‑level sign‑off efforts, we’d like to meet you.

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- 10+ years of ASIC/SoC Physical Design / APR experience in a reputed product company, with multiple tapeouts.
- Senior Block Coordinator responsible for planning/execution and closure of 15+ blocks.




- Strong hands-on expertise in Cadence Innovus: floorplan, place/opt, CTS, route, and ECO closure at block level.
- Proven ability to drive timing closure (setup/hold), MMMC, constraints/exceptions alignment, and QoR improvement across blocks.
- Solid experience in congestion/routability debugging (macro placement/pin access/blockages/density) and driving closure actions with transparent metrics.
- Experience across advanced and lower/mature nodes (e.g., 2/3/4/6nm).
- Strong understanding of block signoff readiness and coordination for DRC/LVS, SI-aware optimization, and IR/EM closure with signoff teams.
- Mandatory scripting/automation: strong Tcl (Innovus) for flow execution, report parsing, and QoR tracking; Python/Perl/Shell preferred.
- Strong cross-team coordination with STA/DFT/Synthesis/CAD.

📌 Senior/Staff Physical Design Engineer (Bengaluru)
🏢 MediaTek
📍 Bengaluru