Senior Layout Design Engineer

Location: Bengaluru

Experience: 3–7 Years

Role Overview

We are looking for an experienced Analog Layout Design Engineer with hands-on expertise in eFuse macro layout and a robust understanding of SRAM layout design. The ideal candidate should have solid fundamentals in full-custom IC layout, physical verification and transistor-level layout implementation.

Key Responsibilities

- Develop and implement full-custom eFuse macro layouts.
- Perform transistor-level layout, placement and routing of eFuse circuits.
- Work on SRAM layout blocks with an understanding of bitcells and memory peripheral circuits.
- Execute physical verification activities, including DRC, LVS and ERC.
- Perform layout debugging, optimization and physical verification closure.
- Collaborate with circuit design and memory design teams to ensure layout meets design specifications.




- Follow technology-specific layout rules and reliability guidelines.

Required Skills

- 3–7 years of hands-on experience in Custom IC / Analog Layout.
- Direct experience in eFuse macro layout design.
- Good understanding of SRAM layout design and memory architecture.
- Strong knowledge of transistor-level layout and CMOS fundamentals.
- Hands-on experience with Cadence Virtuoso.
- Good understanding of DRC, LVS, ERC and parasitic extraction.
- Exposure to advanced CMOS technology nodes and layout design methodologies.

Preferred Skills

- Exposure to OTP / MTP / NVM layout.
- Understanding of SRAM bitcells, sense amplifiers and memory peripheral circuits.
- Experience with Mentor Graphics Calibre.
- Exposure to FinFET technology nodes.

📌 Senior Layout Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru