Senior IO Layout Engineer

Location: Bengaluru

Experience: 5–10 Years

Role Overview

We are looking for a highly skilled Senior IO Layout Engineer with solid hands-on experience in full-custom analog/mixed-signal and high-speed IO layout design across advanced semiconductor technology nodes. The ideal candidate should have expertise in FinFET technologies, advanced-node physical layout, parasitic optimization, and layout implementation for 2nm, 3nm, and 5nm process nodes.

Key Responsibilities

- Own full-custom IO layout development for high-speed and high-performance IO circuits.
- Execute transistor-level layout for analog, mixed-signal, and IO IP blocks.
- Drive layout implementation across advanced technology nodes (2nm, 3nm, 5nm FinFET).
- Implement critical layout techniques including matching, symmetry, shielding, guard rings, and noise isolation.
- Perform floorplanning, device placement, routing, and parasitic optimization.
- Ensure compliance with DRC, LVS, ERC, antenna, and density requirements.
- Work closely with Analog Design, IO Design, Circuit Design, and Physical Verification teams.
- Drive layout optimization for signal integrity, reliability, electromigration, and IR drop.
- Debug complex physical verification issues and drive layout closure.




- Contribute to layout methodologies and best practices for advanced-node technologies.

Required Technical Skills

- 5–10 years of hands-on experience in custom IC / Analog / IO Layout.
- Strong experience in FinFET technology nodes – 5nm, 3nm, and/or 2nm.
- Expertise in full-custom layout for IO circuits and analog/mixed-signal IPs.
- Strong understanding of transistor-level layout, matching, symmetry, and parasitic effects.
- Hands-on experience with DRC, LVS, ERC, antenna checks, and physical verification.
- Proficiency in industry-standard EDA tools:
- Cadence Virtuoso Layout Suite
- Synopsys Custom Compiler
- Calibre DRC/LVS
- Strong understanding of advanced-node layout constraints, design rules, and foundry requirements.
- Experience in layout debugging, parasitic extraction, and physical verification closure.

Preferred Qualifications

- Experience in high-speed IO interfaces such as PCIe, DDR, USB, Ethernet, or SerDes.
- Exposure to advanced FinFET process technologies and complex IO architectures.
- Understanding of ESD protection, latch-up prevention, and reliability constraints.
- Experience working with global semiconductor / product engineering teams.

📌 Senior IO Layout Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru