03 Nov
|
CoreEl Technologies
|
Bengaluru
03 Nov
CoreEl Technologies
Bengaluru
Key ResponsibilitiesDevelop RTL designs using Verilog/VHDL
Implement FPGA-based signal processing and control logic
Perform simulation, verification, synthesis, and timing closure
Work with Xilinx FPGA platforms and Zynq SoCs
Support hardware integration, testing, and debugging
Collaborate with Hardware, Firmware, and System Engineering teams
Required SkillsFPGA Design & Development
Verilog / VHDL
Xilinx Vivado Tool Flow
ModelSim / XSIM
Static Timing Analysis (STA)
Zynq / Zynq UltraScale+ Platforms
Tcl/Python/Shell Scripting
Preferred ExperienceDSP implementation for Wireless Communication or Radar Systems
MATLAB/Octave Modelling
ADC/DAC Interface Design
FPGA Debugging and Board Bring-up
📌 Senior FPGA RTL Design Engineer (Bengaluru)
🏢 CoreEl Technologies
📍 Bengaluru