03 Nov
|
Modernize Chip Solutions (MCS)
|
Hyderabad
03 Nov
Modernize Chip Solutions (MCS)
Hyderabad
Job Title: Design Verification Engineer – Gate-Level Simulation (GLS)
Experience: 4–5 Years
Location: Hyderabad
Notice Period: Immediate to 15 Days Only
Mandatory Skills:
- Strong experience in Design Verification (DV).
- Hands-on experience in Gate-Level Simulation (GLS).
- Robust knowledge of Verilog and SystemVerilog.
- Experience in simulation, debugging, and failure analysis.
- Good understanding of timing concepts and SDF annotation.
- Strong debugging and problem-solving skills.
- Must have worked on a minimum of 3 GLS projects.
Interested candidates can share their updated resumes to:
[email protected]
📌 Design Verification Engineer – Gate-Level Simulation (GLS) (Hyderabad)
🏢 Modernize Chip Solutions (MCS)
📍 Hyderabad