Job Summary:

CYIENT SEMICONDUCTORS PRIVATE LIMITED is seeking a highly motivated and skilled Digital Design Engineer to contribute to the full lifecycle of ASIC/SoC Design implementation. This role involves tackling complex design challenges in advanced technology nodes and ensuring high-performance, low-power, and area-optimized designs.

Responsibilities:
RTL development using VHDL or Verilog/System Verilog, according to functional requirements and following design guidelines
Lint, CDC, Synthesis, & Power Optimization
Soft and hard IP identification, selection and integration
Timing and power constraints development
Collaboration with analog design team for mixed-signal designs
Collaboration with verification team in verification plan development and debug
Collaboration with physical design team to close the design on timing and power




Collaboration with firmware design team to close the design system scenarios

Minimum Qualification:
15:18 years' experience in RTL development
Advanced knowledge of RTL design using VHDL or Verilog/SystemVerilog
Low power (UPF) implementation. RTL sing-off.
Experience working closely with Firmware, Verification, DFT & PD team
Solid communication and presentation skills in English.

Preferred Qualification:
Hands-on experience with synthesis.
Able to work in a team
Valuable problem solving skills and being able to implement solutions autonomously
Knowledge of mixed signal concepts (added advantage)

📌 Digital Design Engineer Bengaluru
🏢 Cyient
📍 Bengaluru