Staff DFT Engineer

Top20 Semiconductor Organization in the world

Bangalore

We are a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. combine analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $10 billion in FY25, we ensure today's innovators stay Ahead of What's Possible.

Job Description:

We are seeking a skilled and experienced DFT Engineer to join our VLSI design team. The ideal candidate should have a strong background in Design for Testability (DFT) techniques, including LBIST (Logic Built-In Self-Test), ATPG (Automatic Test Pattern Generation), DFT DRC (Design Rule Checking), MBIST (Memory Built-in Sefl-Test), Boundary Scan, JTAG and Analog/Phy DFT.

Responsibilities:

- Collaborate with the Design/Arch/PTE/PD team to ensure efficient and effective testability of complex integrated circuits.
- Design and implement DFT features such as scan chains, compression, and built-in self-test structures to enhance testability.
- Conduct DFT DRC checks in RTL/Netlist database to ensure compliance with DFT guidelines and rules.
- Utilize Siemen's DFT tool to perform DFT analysis and optimize testability metrics.
- Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models using on-chip test compression techniques.
- MBIST Design (including repair) and Verification using Siemen's EDA tool.
- Validation of DFT structures/patterns in RTL, Netlist with and without SDF.
- Work closely with the verification team to define and implement DFT verification plans.




- Work closely with physical design team for DFT implementation/constraints strategy for synthesis/STA.
- Analyze and debug test failures and collaborate with the test engineering team to resolve issues.
- Provide guidance and mentorship to junior DFT engineers.

Qualifications:

- Bachelor's/Master's degree in Electrical/Electronic Engineering, or a related field.
- 7-12 years of hands-on experience in DFT methodologies and techniques.
- Strong knowledge of LBIST, ATPG, DFT DRC, Scan compression, Low power DFT Techniques, MBIST, Boundary Scan, Analog DFT, JTAG Architecture, DFT STA Constraint development.
- Hand-on experience/expertise in Cadence/Siemen's DFT EDA tools for Scan stitching, DRC, ATPG, Coverage improvement, MBIST, Boundary Scan.
- Proficiency in scripting languages such as Perl, Tcl, and/or Python for automation.
- Solid understanding of digital design fundamentals, RTL coding, Lint/CDC, Low Power Checks and ASIC design flow.
- Excellent problem-solving skills and ability to work effectively in a team-oriented environment.
- Strong communication and interpersonal skills.

Why You'll Love Working Here

At you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on skilled growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.

Your expertise will shape the future of technology, and you'll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.

Contact:Uday

Mulya Technologies

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📌 Staff DFT Engineer (Gandhinagar)
🏢 Mulya Technologies
📍 Gandhinagar