The Job Role:

- We are looking for profiles with strong understanding of STA concepts and Timing constraints with 6-15 years of experience

Job Responsibility:

- Must have solid understanding of timing constraints and their verification at SoC and block level along with valuable understanding of STA concepts to debug timing constraint issues.
- This role will provide SoC and block level timing constraints development exposure.
- Responsibilities will include promotion of multiple IP timing constraints' to SoC level and integrating them into SoC timing constraints.

Required Skills:

- Understanding of STA concepts and Timing constraints as well as VLSI design flow;

Familiarity with Verilog, timing (.lib), LEF, GDS; Familiarity with physical design verification, e.g. DRC and LVS; Ability to execute and modify scripts in PERL, Unix shell, Tcl, Python or related language. 3-6 years of experienceRole & responsibilities

Preferred candidate profile

Perks and benefits

📌 STA engineer (Hyderabad)
🏢 Proxelera
📍 Hyderabad