Job Description
Roles & Responsibilities
Handle parametric and functional verification activities for analog and mixed-signal designs.
Work with Cadence Virtuoso ADE-XL for design verification and analysis.
Use verification tools such as Incisive, vManager and vPlanner.
Work with simulation tools including Spectre, AFS and VCS-AMS.
Support FastSPICE simulation using Spectre, CustomSim and FineSimPro.
Develop and maintain automation scripts using TCL, Shell, Perl, Cadence SKILL and Python.
Collaborate with design and verification teams to support design enablement activities.
Support IT infrastructure and LSF-related requirements for design environments.
Preferred Candidate Profile
12+ years of relevant experience in Analog Front-End / Design Enablement.
Solid experience in parametric and functional verification.
Hands-on experience with Cadence Virtuoso ADE-XL.
Experience with Incisive, vManager, vPlanner, Spectre, AFS or VCS-AMS.
Knowledge of Wreal, SystemVerilog, Verilog-AMS, UVM and UNL.
Experience with FastSPICE tools such as CustomSim and FineSimPro.
Strong scripting knowledge in TCL, Shell, Perl, Cadence SKILL or Python.
Exposure to IT infrastructure and LSF job scheduling.

📌 Analog FE / Design Enablement Engineer (Bengaluru)
🏢 Allegis Global Solutions (AGS)
📍 Bengaluru