Senior Analog Layout Engineer

Location: Hyderabad, India

Experience: 4–8 Years

Role Overview

We are looking for a skilled Senior Analog Layout Engineer with robust hands-on expertise in custom analog and mixed-signal IC layout development across advanced technology nodes. The ideal candidate should have proven experience in FinFET technologies, particularly 2nm, 3nm, 5nm and other advanced process nodes, with strong ownership of block-level layout, physical verification and tapeout execution.

Key Responsibilities

- Develop high-quality custom layouts for analog, mixed-signal and high-performance IP blocks.
- Execute transistor-level layout with strong expertise in matching, symmetry, common-centroid and interdigitation techniques.
- Drive layout implementation across advanced FinFET technology nodes (2nm, 3nm, 5nm and below).
- Perform floorplanning, placement, routing and parasitic-aware layout optimization.
- Ensure DRC, LVS, ERC and other physical verification signoff compliance.
- Optimize layouts for area, performance, power, signal integrity and reliability.
- Work closely with Analog Design,



Circuit Design and Physical Verification teams to resolve layout-related issues.
- Support post-layout simulation, parasitic extraction and tapeout signoff.

Required Technical Skills

- 4–8 years of hands-on experience in Analog / Custom IC Layout Design.
- Strong exposure to advanced technology nodes: 2nm, 3nm, 5nm, FinFET and lower nodes.
- Expertise in Analog and Mixed-Signal layout methodologies.
- Strong understanding of matching, shielding, guard rings, latch-up prevention and noise isolation.
- Hands-on experience with DRC, LVS, ERC and PEX.
- Proficiency in industry-standard EDA tools such as Cadence Virtuoso and relevant physical verification tools.
- Understanding of advanced process design rules, parasitic effects and layout-dependent effects (LDE).

Preferred Qualifications

- Experience in high-speed analog, PLL, ADC/DAC, SerDes, Power Management or other custom analog IP layouts.
- Exposure to advanced FinFET layout constraints and complex routing methodologies.
- Strong debugging, problem-solving and cross-functional collaboration skills.

📌 Senior Analog Layout Engineer (Hyderabad)
🏢 Leadsoc Technologies
📍 Hyderabad