Hiring: Memory Layout Engineers & Memory Design Engineers | Aritrak Technologies |

Location: Bangalore / Hyderabad

Experience: 2–12 years

Notice Period: Immediate to 30 days

We are looking for experienced Memory Layout and Memory Design Engineers to contribute to memory IP development across advanced technology nodes.

- Memory Layout Engineer

Key Responsibilities: Develop full-custom layouts for memory blocks, including bitcells, arrays and peripheral circuits.
- Perform floorplanning, placement, routing and layout optimization to meet area and performance targets.
- Execute physical verification, including DRC, LVS, ERC and antenna checks.
- Work with circuit designers to address parasitic effects, matching and layout-dependent issues.
- Support extraction, EM/IR analysis, debugging and final layout signoff.
- Required SkillsHands-on experience in SRAM or other embedded memory layouts.
- Robust understanding of full-custom layout techniques, device matching, shielding and reliability requirements.
- Experience with Cadence Virtuoso and physical verification tools such as Calibre, PVS or equivalent.
- Familiarity with advanced CMOS/FinFET technology nodes and foundry design rules.
- Experience with memory compiler layouts and layout automation is an advantage.

- Memory Design Engineer

Key Responsibilities

Design and simulate transistor-level memory circuits,



including bitcells and peripheral blocks.
- Develop circuits such as decoders, sense amplifiers, write drivers and control logic.
- Optimize memory performance, power, area and operating margins.
- Perform PVT corner simulations, Monte Carlo analysis and post-layout verification.
- Collaborate with layout engineers to resolve parasitic effects and achieve design closure.
- Support memory characterization, debugging and design documentation.
- Required SkillsHands-on experience in SRAM or other embedded memory circuit design.
- Strong understanding of CMOS circuits, memory architecture, read/write operations and stability margins.
- Experience with Cadence Virtuoso and circuit simulation tools such as Spectre, HSPICE or equivalent.
- Knowledge of timing, leakage, dynamic power and variation analysis.
- Familiarity with memory characterization and compiler development is an advantage.

Qualification: B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI or a related discipline.Candidates with greater experience should be comfortable owning technical delivery, reviewing designs and mentoring engineers.

Apply: Share your CV at [email protected] with your preferred role, location, total experience and notice period.

📌 Memory Layout & Memory Design Engineer (Bengaluru)
🏢 Aritrak Technologies Private
📍 Bengaluru