12 Nov
|
Source right
|
Hyderabad
12 Nov
Source right
Hyderabad
Position: DFT (ST36FT RM 4596)
Mode Of Interview : In-Person/Virtual
Qualifications : B.Tech/MTech
Please note that candidates will be required to work at the client’s location
- Looking for candidates with 4 to 6 years Experience
- Accountable for creative DFT implementation(Scan, MBIST, LBIST & Boundary Scan) at the RTL and Gate level for a given SOC at Hard macro and chip top level.
- Shall have experience with EDT OCC insertion at RTL and Gate level along with Scan stitching.
- Generate and validate ATPG patterns using simulations.
- Shall Validate the DFT implementation using RTL and Gate level simulation.
- Work with Multi-functional Teams on STA, Synthesis, LEC, CLP, verification & Validation.
- Must have experience with Siemens, Synopsys and/or Cadence Cad tools.
- Shall have experience in coding with Verilog, VHDL, C/C++, TCL, Perl and or Python
📌 DFT EngineerFT RM 4596) (Hyderabad)
🏢 Source right
📍 Hyderabad