Company Description BigEndian Semiconductors is a fabless semiconductor startup building secure, high-performance System-on-Chips (SoCs) in India for global markets. The company focuses on silicon platforms that power next-generation surveillance, telecom, IoT, and enterprise systems, driven by a “security by design” philosophy that tightly integrates hardware and software. With deep expertise in VLSI, system architecture, and embedded software, BigEndian delivers trusted solutions that support both national security and commercial applications.

Headquartered in Bengaluru and supported by strategic partnerships in Taiwan and India, the company is backed by a leadership team with decades of experience at organizations such as Intel, ARM, Broadcom, and Zenoti. BigEndian is committed to advancing India as a global hub for semiconductor design, innovation, and manufacturing.

Role Description As a DFT Engineer at BigEndian Semiconductors, you will be responsible for designing and implementing Design-for-Test (DFT) architectures for complex SoCs, including scan insertion, boundary scan, memory BIST, and logic BIST. You will collaborate closely with front-end and back-end design teams to integrate DFT features, optimize test coverage, and ensure minimal impact on performance, power, and area. Day-to-day activities include developing test plans, generating and validating test patterns, running simulations,



analyzing coverage reports, and supporting silicon bring-up and production test.

You will also work with external test houses and internal stakeholders to debug test failures, refine DFT methodologies, and contribute to continuous improvement of the test infrastructure. This is a full-time, on-site role based in Bengaluru.

Qualifications

- Strong test engineering capabilities, including experience in Test Engineering and Testing for digital ICs or SoCs.
- Proficiency in defining and managing Test Cases and executing Test Execution flows for functional and structural tests.
- Hands-on experience with Functional Testing, simulation-based verification, and coverage analysis for DFT features.
- Solid understanding of DFT concepts such as scan architectures, JTAG/IEEE 1149.x, MBIST/LBIST, and ATPG tools.
- Experience with industry-standard EDA tools (e.g., Synopsys, Cadence, or Mentor) for DFT insertion and pattern generation.
- Valuable knowledge of digital design fundamentals, Verilog/SystemVerilog, and basic scripting (Python, Perl, or TCL) for automation.
- Ability to collaborate in cross-functional teams, communicate clearly, and document test plans and results effectively.
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or a related field; prior semiconductor or SoC experience is highly beneficial.

📌 DFT Engineer (Bengaluru)
🏢 BigEndian Semiconductors
📍 Bengaluru