DFT Engineer – ATPG & MBIST

Company: LeadIC Design Pvt Ltd

Experience: 3–6 Years

Employment Type: Full-time

Locations: Bengaluru, Karnataka / Hyderabad, Telangana

Work Mode: On-site

Notice Period: Immediate to 30 Days

LeadIC Design Pvt Ltd is seeking skilled DFT Engineers with 3–6 years of hands-on experience in Design for Testability, Scan Insertion, ATPG and MBIST for SoC/ASIC designs.

Key Responsibilities:

- DFT architecture, implementation and integration.
- Scan insertion, scan-chain configuration and scan compression.
- ATPG pattern generation, simulation and coverage analysis.
- Stuck-at and transition fault testing.
- MBIST architecture, implementation and verification.
- Memory testing, BIRA, BISR and memory repair.
- JTAG, IJTAG, TAP and APB-based MBIST access integration.
- SoC-level DFT integration and ATPG pattern retargeting.




- DFT debugging and test coverage improvement.

Required Skills:

- 3–6 years of relevant DFT experience.
- Robust hands-on experience in Scan Insertion and ATPG.
- Practical experience with MBIST and memory testing.
- Knowledge of BIRA, BISR and memory repair.
- Understanding of JTAG, IJTAG and IEEE 1500.
- Experience with SoC DFT integration and verification.
- Scripting knowledge in Tcl, Python or Perl.

Candidate Requirements:

- Immediate joiners to 30 days' notice period preferred.
- Willingness to work on-site in Bengaluru or Hyderabad.

Apply: Share your updated resume at [email protected]

📌 DFT Engineer | 2+ Yrs (Bengaluru)
🏢 leadIC Design
📍 Bengaluru