Job Summary

Define ASIC/SoC verification strategy Good understanding of ASIC/SoC life cycle Full chip testplan development Experience writing ASIC/SoC testplans Full chip TB Architecture definition Experience in writing verification strategy document UVM based testbench development 1.Experience in ASIC/SoC Testbench definition 2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM). C based TB development 1. Experience in developing TB components for SOC with C, SV SV functional coverage, Assertions coding 1.Expertise & hands-on experience in OVM/UVM methodologies using SV 2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans. Test case development, coding, execution, bug analysis 1. Experience in developing TB components, including functional coverage implementation and assertion coding 2.



Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic. 3.Debug c

Key Responsibilities

1. To work closely with stakeholders to understand and refine design requirements.
2. To develop prototypes and proof-of-concept implementations to validate design decisions.
3. To mentor junior designers ,share knowledge and expertise through training sessions and documentation.
4. To collaborate with cross functional teams and other stakeholders to align software design with overall project goals.
5. To work with quality assurance teams to establish and maintain high-quality.

Skill Requirements

null

Must Have Skill

SoC,System Verilog

Positive to Have Skill

Other Requirements

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📌 Senior Designer (Bengaluru)
🏢 HCLTech
📍 Bengaluru